Embodiments of the present disclosure are directed to a semiconductor memory device and a method of fabricating the same, and in particular, to a semiconductor memory device that includes buried gate lines and a method of fabricating the same.
Due to their small-sized, multifunctional, or low-cost characteristics, semiconductor devices are important elements in the electronic industry. Semiconductor devices can be classified into semiconductor memory devices for storing data, semiconductor logic devices for processing data, and hybrid semiconductor devices that include both memory and logic elements.
Due to increasing demand for high speed low-power electronic devices, semiconductor devices require a fast operating speed or a low operating voltage. To satisfy this demand, a semiconductor device needs a high integration density, that is, more elements per area. However, an increase in the integration density can lead to a decrease in the reliability of the semiconductor device.
In a dual work function metal gate structure, a tungsten electrode is provided at a lower level, and an n-doped poly-silicon is provided at an upper level. In this structure, owing to a subsequent thermal treatment process, intermixing between the two materials can occur. To prevent this intermixing, a barrier layer having a low resistance property is used.
In a conventional technology, a SiO2-based material is used as the barrier layer. If such a SiO2-based barrier layer has a thickness of 10 Å or more, it can act as an insulating layer, which can lead to a deterioration of the electric characteristics of the semiconductor device. In some cases, the barrier layer is formed by directly depositing a TiN-based metal layer and removing a sidewall portion thereof. However, in these cases, it is challenging to control dispersion errors while depositing and removing the metal layer. Moreover, during the deposition process, metal contamination can occur in a sidewall portion of a gate oxide.